This invention relates to a semiconductor device comprising a plurality of wiring layers which are laminated on a silicon substrate. Such a semiconductor device is particularly useful in an LSI (large-scale integrated circuit).
In manufacture of a semiconductor device suitable for an LSI, it is required to laminate wiring layers on a silicon substrate as many as possible. Let first through third wiring layers be laminated on the silicon substrate. The first wiring layer comprises a first insulator layer formed on the silicon substrate, circuit patterns formed on the first insulator layer by conductive material. The second wiring layer comprises a second insulator layer, circuit patterns formed on the second insulator layer. Similarly, the third wiring layer comprises a third insulator layer, circuit patterns formed on the third insulator layer. The second insulator layer is formed on the first wiring layer so as to cover an upper surface of the first insulator layer and the circuit patterns of the first wiring layer. Similarly, the third insulator layer is formed on the second wiring layer so as to cover an upper surface of the second insulator layer and the circuit patterns of the second wiring layer. Each of the second and the third insulator layers may be called an interlayer insulator layer. The circuit patterns in the first through the third wiring layers are connected to one another by the use of connection means, such as a through hole, so as to form a required circuit.
With respect to the first wiring layer, the circuit patterns are spaced apart from one another by at least a predetermined pitch Lp and have pattern widths which are not narrower than a predetermined minimum width Lw. In general, the first insulator layer inevitably has a vacant area outside the circuit patterns. Such a vacant area causes a step portion or a hollow portion on an upper surface of the second insulator layer that is formed on the first wiring layer. Such a hollow portion causes degradation of workability for forming the circuit patterns of the second wiring layer or breaking of the circuit patterns of the second wiring layer. This phenomenon applies to the third wiring layer. Such a disadvantage becomes remarkable as the number of wiring layers increases.
In order to get rid of the disadvantage mentioned above, the following manner is well known in the art. For example, a plurality of dummy patterns are formed on the vacant area of the insulator layer in the wiring layer. As an example of the dummy patterns, strip dummy patterns are formed in parallel with the circuit patterns at the intervals of the predetermined pitch Lp. Each of the strip dummy patterns has a large area. This means that wiring capacity caused by the strip dummy patterns becomes large. In this event, if one of the strip dummy patterns are connected to a part of the circuit patterns by mistake, it causes increment of a delay time in the required circuit. As another example of the dummy patterns, square dummy patterns are regularly formed on the vacant area at the intervals of the predetermined pitch Lp. Each of the square dummy patterns has a side equal to the minimum pattern width Lw. In this event, the square dummy patterns are apt to peel from the insulator layer because the side in the square dummy patterns is too short.
Taking the above into consideration, rectangular dummy patterns are regularly formed on the vacant area at intervals of the predetermined pitch Lp. As will later be described in detail, each of the rectangular dummy patterns has a pair of short sides which are equal, in size, to the minimum pattern width Lw. Although the rectangular dummy patterns are superior to the strip dummy patterns and the square dummy patterns, it is hard to perfectly dissolve the problem of the hollow portion mentioned above. For the reason mentioned above, it is hard to realize the semiconductor device comprising a plurality of wiring layers which are more than four layers.